CY7C455 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

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CY7C455
CY7C456
CY7C457
512 x 18, 1K x 18, and 2K x 18 Cascadable
Clocked FIFOs with Programmable Flags
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 18 (CY7C455)
• 1,024 x 18 (CY7C456)
• 2,048 x 18 (CY7C457)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — I_CC=90 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 52-pin PLCC and 52-pin PQFP
Functional Description
The CY7C455, CY7C456, and CY7C457 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features in-
clude Almost Full/Empty flags and generation/checking of par-
ity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
Logic Block Diagram
D_{0 – 17}
INPUT
REGISTER
CKW
ENW
WRITE
CONTROL
PARITY
MR
FL/RT
XI
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
RETRANSMIT
LOGIC
RAM
ARRAY
512 x 18
1024 x 18
2048 x 18
THREE–STATE
OUTPUT REGISTER
OE
Q_{0 – 7}, Q₈/PG1/PE1
Q_{9– 16}, Q17/PG2/PE2
Pin Configurations
PLCC
Top View
FLAG/PARITY
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
D₂
D₁
D₀
XI
HF
ENW
E/F
CKW
PAFE/XO HF
E/F
XO/PAFE
Q₀
Q₁
Q₂
Q₃
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
7C455
41
14
7C456
40
15
7C457
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
D₁₃
D₁₄
D₁₅
D₁₆
D₁₇
FL/RT
MR
CKR
ENR
OE
Q₁₇/PG2/PE2
Q₁₆
Q₁₅
READ
CONTROL
CKR
ENR ^c455-1
c455-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06003 Rev. *A
Revised December 26, 2002