CY7C455 Datasheet, PDF (15/23 Pages) Cypress Semiconductor – 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

Switching Waveforms (continued)
[41]
Even Par ity Checking
CKW
WRITE M
WRITE M+1
WRITE M+2
ENW
CY7C455
CY7C456
CY7C457
D_0−
7
WORD M:
EVEN NUMBER
OF 1“ s
WORD M+ 1:
ODD NUMBER
OF 1“ s
CKR
WORD M+ 2:
EVEN NUMBER
OF 1“s
ENR
F₁
PE₁
(PE₂)
Q_{0− 7}
(Q_{9− 16})
Output Enable Timing^{[42, 43]}
CKR
ENR
LOW
OE
Q_{0− 17}
VALID DATA
WORD M
Retransmit Timing^{[44, 45]}
FL/RT
t_OHZ
REN/WEN
READ M
READ M+1
READ M+2
t_PE
t_PE
8 LSBs OF
WORD M-1
8 LSBs OF
WORD M
8 LSBs OF
WORD M+1
READ M+1
8 LSBs OF
WORD M+2
c455-23
t_OE
t_OLZ
t_PRT
VALID DATA
WORD M+1
c455–24
t_RTR
E/F, HF, PAFE
42X5–21
Notes:
41. In this example, the FIFO is assumed to be programmed to check for even parity. The Q_0-7 word is shown.
42. This example assumes that the time from the CKR rising edge to valid word M+1 > t_A. The Q_0-7 word is shown.
43. If ENR was HIGH around the rising edge of CKR (i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1.
44. Clocks are free running in this case.
45. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t_RTR.
Document #: 38-06003 Rev. *A
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