CY7C455 Datasheet, PDF (10/23 Pages) Cypress Semiconductor – 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[22, 25, 27]
Read to Almost Empty Timing Diagram with Free-Running Clocks
COUNT
17
16
17
18
17
CKR
R1
R2
ENABLED
READ
R3
R4
ENABLED
READ
ENR
CKW
t_SKEW1
W1
W2
ENABLED
WRITE
t_SKEW2
W3
W4
ENABLED
WRITE
ENW
16
R5
ENABLED
READ
W15
15
R6
ENABLED
READ
W6
HF
HIGH
E/F
HIGH
t_FD
t_FD
t_FD
PAFE
c455-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks ^{[22, 25, 27, 28, 29]}
COUNT 17 16
CKR
R1
ENABLED
READ
ENR
CKW
t_SKEW1
W1
ENW
17
R2
W2
ENABLED
WRITE
18
R3
18 (no change)
FLAG UPDATE CYCLE ₁₇
R4
FLAG
UPDATE
READ
R5
ENABLED
READ
16
R6
ENABLED
READ
t_SKEW2
W3
W4
ENABLED
WRITE
W5
W6
15
R7
ENABLED
READ
W7
HF ^HIGH
E/F ^HIGH
t_FD
t_FD
t_FD
PAFE
c455-13
Notes:
27. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full.
28. R4 only updates the flag status. It does not affect the count because ENR is HIGH.
29. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 Á18; two enabled writes: W2, W3) before a read (R4)
can update flags to the Less Than Half Full state.
Document #: 38-06003 Rev. *A
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