IBIS4-1300_09 Datasheet, PDF (17/37 Pages) Cypress Semiconductor – 1.3 MPxl Rolling Shutter CMOS Image Sensor

IBIS4-1300
Figure 11. shows the output characteristic curve in a typical
case for the imager. The offset voltage is adjusted to 2 V, which
corresponds to the low-level voltage of the ADC. Clipping is
off, and the input signal is changed between 0 and 5 V. During
offset adjustment (when calib_s is switched from 1 -> 0 or
when calib_f is on), the input signal is at 1.2 V. This level corre-
sponds to the imager dark reference output. The input signal
is transferred to the output by adding a 2V offset and multipli-
cation with the appropriate gain. The input signal of dark pixels
(at 1.2 V) corresponds with 2 V at the output. Higher input
signals are amplified. The curves for 3 typical gain settings are
shown (unity gain, setting 3, 7 & 11).
Again, as can be seen on the above figure, the applied input
signal during the output amplifier calibration (by 'CALIB_S' or
'CALIB_F') is the reference level to which the signal is
amplified. During this calibration, a stable input is required.
Setting of the VLOW_DAC & VHIGH_DAC reference voltages
Figure 12. suggested circuit for high and low references of DAC
VHIGH_DAC
About 2.3 V
VLOW_DAC
About 1 V
VLOW_DAC & VHIGH_DAC are the reference voltages for the
DAC. They represent the 0000 resp. 1111 code. The internal
series resistance is about 1.3 kOhms. They can be connected
as in Figure 12., and decoupled to ground.
Table 6. ADC specifications
Input range
Quantization
Nominal data rate
DNL (linear conversion mode)
INL (linear conversion mode)
Input capacitance
Power dissipation @ 10 MHz
Delay of digital circuitry (Td, 40 pF load)
Input setup time (Ts) for a stable LSB
Conversion law
Analog to digital converter
The IBIS4-1300 has a 10 bit flash analog digital converter
running nominally at 10 Msamples/s. The ADC is electrically
separated from the image sensor. The input of the ADC
("IN_ADC") should be tied externally to the OUTPUT of the
output amplifier.
2-4V
10 Bits
10 Msamples/s (*)
< 20 pF
107 mA
535 mW
< 50 ns after falling edge of clock
< 100 ns before falling edge of clock
Linear / Gamma-corrected
(*) Project partners have demonstrated 20 MHz data rate by
careful timing and by decreasing some or all of the resistors
on NBIAS* and PBIAS*.
Document Number: 38-05707 Rev. *B
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