W150_03 Datasheet, PDF (12/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)
Parameter
Description
t_F
Output Fall Edge Rate
t_D
Duty Cycle
t_SK
Output Skew
t_PD
Propagation Delay
Z_o
AC Output Impedance
Test Condition/Comments
Measured from 2.4V to 0.4V
Measured on rising and falling edge at
1.5V
Measured on rising and falling edge at
1.5V
Measured from SDRAMIN
Average value during switching
transition. Used for determining series
termination value.
CPU = 66.8 MHz
Min. Typ. Max.
1
4
45
55
CPU = 100 MHz
Min. Typ. Max.
1
4
45
55
Unit
V/ns
%
250
250 ps
3.7
3.7
ns
15
15
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f_D
Deviation from 48 MHz
m/n
PLL Ratio
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
CPU = 66.8/100 MHz
Test Condition/Comments
Min. Typ. Max. Unit
Determined by PLL divider ratio (see m/n below)
48.008
MHz
(48.008 – 48)/48
+167
ppm
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
Measured from 0.4V to 2.4V
0.5
2 V/ns
Measured from 2.4V to 0.4V
0.5
2 V/ns
Measured on rising and falling edge at 1.5V
45
55 %
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3 ms
Average value during switching transition. Used for deter-
25
Ω
mining series termination value.
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 24 MHz (24.004 – 24)/24
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold power-up. Short cycles exist prior to frequency stabili-
start)
zation.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
CPU = 66.8/100 MHz
Min. Typ. Max.
24.004
+167
57/34
0.5
2
0.5
2
45
55
3
25
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Package Type
W150H
56-pin SSOP
W150HT
56-pin SSOP – Tape and Reel
Industrial Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Document #: 38-07177 Rev. *B
Page 12 of 15