W150_03 Datasheet, PDF (11/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)
Parameter
Description
Test Condition/Comments
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Z_o
AC Output Impedance Average value during switching transition.
Used for determining series termination
value.
CPU = 66.6/100 MHz
Min.
Typ.
Max.
1
4
45
55
250
500
1.5
4
3
15
Unit
V/ns
%
ps
ps
ns
ms
Ω
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Z_o
Description
Test Condition/Comments
Frequency, Actual
Frequency generated by crystal oscillator
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
Duty Cycle
Measured on rising and falling edge at 1.25V
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
14.318
0.5
2
0.5
2
45
55
3
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t
P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
CPU = 66.8 MHz
Min. Typ. Max.
15
15.5
5.2
5.0
1
4
CPU = 100 MHz
Min. Typ. Max.
10
10.5
3.0
2.0
1
4
Unit
ns
ns
ns
V/ns
Document #: 38-07177 Rev. *B
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