W150_03 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

PRELIMINARY
W150
440BX AGPset Spread Spectrum
Frequency Synthesizer
Features
• Maximized electromagnetic interference (EMI)
suppression using Cypress’s Spread Spectrum
technology
• Single-chip system frequency synthesizer for Intel^®
440BX AGPset
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB/one 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• 17 SDRAM outputs provide support for four DIMMs
• Supports frequencies up to 150 MHz
• SMBus interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew:............................................. 500 ps
SDRAMIN to SDRAM0:15 Delay:.......................... 3.7 ns typ.
V_DDQ3: ..................................................................... 3.3V±5%
V_DDQ2: ..................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.
Table 1. Mode Input Table
Mode
Pin 3
0
PCI_STOP#
1
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
FS3 FS2 FS1 FS0
(MHz)
PCI_F, 0:5
(MHz)
1
1
1
1
133.3
33.3 (CPU/4)
1
1
1
0
124
31 (CPU/4)
1
1
0
1
150
37.5 (CPU/4)
1
1
0
0
140
35 (CPU/4)
1
0
1
1
105
35 (CPU/3)
1
0
1
0
110
36.7 (CPU/3)
1
0
0
1
115
38.3 (CPU/3)
1
0
0
0
120
40 (CPU/3)
0
1
1
1
100
33.3 (CPU/3)
0
1
1
0
133.3
44.43 (CPU/3)
0
1
0
1
112
37.3 (CPU/3)
0
1
0
0
103
34.3 (CPU/3)
0
0
1
1
66.8
33.4 (CPU/2)
0
0
1
0
83.3
41.7 (CPU/2)
0
0
0
1
75
37.5 (CPU/2)
0
0
0
0
124
41.3 (CPU/3)
Logic Block Diagram
X1
X2
CLK_STOP#
XTAL
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SMBus
Logic
Stop
Clock
Control
SDRAMIN
PLL2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC_F
IOAPIC0
VDDQ2
CPU_F
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:15
16 _{SDRAM_F}
Pin Configuration^[1]
VDDQ3 1
REF1/FS2 2
REF0/(PCI_STOP#) 3
GND 4
X1 5
X2 6
VDDQ3 7
PCI_F/MODE 8
PCI0/FS3 9
GND 10
PCI1 11
PCI2 12
PCI3 13
PCI4 14
VDDQ3 15
PCI5 16
SDRAMIN 17
SDRAM11 18
SDRAM10 19
VDDQ3 20
SDRAM9 21
SDRAM8 22
GND 23
SDRAM15 24
SDRAM14 25
GND 26
SDATA 27
SCLK 28
56 VDDQ2
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPU_F
51 CPU1
50 VDDQ2
49 CPU2
48 GND
47 CLK_STOP#
46 SDRAM_F
45 VDDQ3
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDQ3
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDDQ3
30 24MHz/FS0
29 48MHz/FS1
Note:
1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function
with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input
FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07177 Rev. *B
Revised January 27, 2003