W144_04 Datasheet, PDF (12/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W144
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Z_o
Description
Test Condition/Comments
Frequency, Actual
Frequency generated by crystal oscillator
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
Duty Cycle
Measured on rising and falling edge at 1.25V
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100.2 MHz
Min. Typ. Max.
14.31818
1
–
4
1
–
4
45
–
55
–
–
1.5
–
15
–
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100.2 MHz
Min. Typ. Max. Unit
14.318
MHz
0.5
–
2 V/ns
0.5 ^–
2 V/ns
45
–
55 %
–
–
3 ms
–
40
–
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
f_D
Deviation from 48 MHz (48.008 – 48)/48
p/q
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold power-up. Short cycles exist prior to frequency stabili-
start)
zation.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100.2 MHz
Min. Typ. Max.
–48.008–
+167
–57/17
0.5
–
2
0.5
–
2
45
–
55
–
–
3
–
40
–
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
f_D
Deviation from 24 MHz (24.004 – 24)/24
p/q
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
CPU = 66.6/100.2 MHz
Min. Typ. Max.
24.004
+167
57/34
0.5
–
2
0.5
–
2
45
–
55
Unit
MHz
ppm
V/ns
V/ns
%
Document #: 38-07153 Rev. *B
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