W144_04 Datasheet, PDF (11/14 Pages) Cypress Semiconductor – 440BX AGPset Spread Spectrum Frequency Synthesizer

W144
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
t_H
High Time
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V,
at min. edge rate (1.5V/ns)
t_L
Low Time
Duration of clock cycle below 0.4V,
at min. edge rate (1.5V/ns
t_R
Output Rise Edge Measured from 0.4V to 2.4V
Rate
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_PLH
Prop Delay LH
Input edge rate faster than 1V/ns
t_PHL
Prop Delay HL
Input edge rate faster than 1 V/ns
t_D
Duty Cycle
Measured on rising and falling edge
at 1.5V,at min. edge rate (1.5 V/ns)
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Covers all CPU/PCI outputs.
Skew
Measured on rising edge at 1.5V.
CPU leads PCI output.
f_ST
Frequency
Assumes full supply voltage
Stabilization from
reached within 1 ms from power-up.
Power-up (cold start) Short cycles exist prior to frequency
stabilization.
Z_o
AC Output
Impedance
Average value during switching
transition. Used for determining
series termination value.
CPU = 66.6 MHz
Min. Typ. Max.
30
–
–
5.6 –
–
5.3 –
–
1.5 –
4
1.5 –
4
1
–
5
1
–
5
45
–
55
–
– 250
–
– 250
1.5 –
4
–
–
3
–
30
–
CPU = 100.2 MHz
Min. Typ. Max. Unit
30 –
– ns
3.3 –
– ns
3.1 –
– ns
1.5 –
4 V/ns
1.5 –
4 V/ns
1
–
5 ns
1
–
5 ns
45 – 55 %
–
– 250 ps
–
– 250 ps
1.5 –
4 ns
–
–
3 ms
–
30
–
Ω
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Z_o
AC Output Impedance Average value during switching transition.
Used for determining series termination
value.
CPU = 66.6/100.2 MHz
Min.
Typ.
Max.
29.9
–
–
12.0
–
–
12.0
–
–
1
–
4
1
–
4
45
–
55
–
–
250
–
–
500
1.5
–
4.0
–
–
3.0
–
30
–
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
Document #: 38-07153 Rev. *B
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