MB9B560R Datasheet, PDF (101/169 Pages) SPANSION – This document states the current technical specifications regarding

MB9B560R Series
12.4.12 UART Timing
Synchronous Serial (SPI = 0, SCINV = 0)
Parameter
Serial clock cycle time
SCK↓→SOT delay time
SIN→SCK↑
setup time
SCK↑→SIN hold time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK↓→SOT delay time
SIN→SCK↑
setup time
SCK↑→SIN hold time
SCK falling time
SCK rising time
Symbo
l
t_SCYC
t_SLOVI
t_IVSHI
t_SHIXI
t_SLSH
t_SHSL
t_SLOVE
t_IVSHE
t_SHIXE
tF
tR
Pin
Name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Condition
s
Internal shift
clock
operation
V_CC < 4.5 V
Min
Max
4t_CYCP
-
- 30
+ 30
50
-
0
-
2t_CYCP - 10
-
t_CYCP + 10
-
-
50
External shift
clock
10
-
operation
20
-
-
5
-
5
(V_CC = 2.7V to 5.5V, V_SS = 0V)
V_CC ≥ 4.5 V
Min
Max
Unit
4t_CYCP
-
ns
- 20
+ 20
ns
30
-
ns
0
-
ns
2t_CYCP - 10
-
ns
t_CYCP + 10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Notes:
• The above characteristics apply to CLK synchronous mode.
• t_CYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance C_L = 30 pF.
Document Number: 002-04864 Rev.*A
Page 101 of 169