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MB9B560R Datasheet, PDF (1/169 Pages) SPANSION – This document states the current technical specifications regarding | |||
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MB9B560R Series
32-Bit ARM® Cortex® - M4F
FM4 Microcontroller
Devices in the MB9B560R Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
This series is based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
Features
32-bit ARM® Cortex®-M4F Core
ï®Processor version: r0p1
ï®Up to 160 MHz Frequency Operation
ï®FPU built-in
ï®Support DSP instruction
ï®Memory Protection Unit (MPU): improves the reliability of an
embedded system
ï®Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
ï®24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
ï®Flash memory
These series are based on two independent on-chip Flash
memories.
ï¯ MainFlash memory
⢠Up to 1024 Kbytes
⢠Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
⢠The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
⢠Security function for code protection
ï¯ WorkFlash memory
⢠32 Kbytes
⢠Read cycle:
⢠6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
⢠4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
⢠2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
⢠0wait-cycle: the operation frequency up to 40 MHz
⢠Security function is shared with code protection
ï® SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
ï¯ SRAM0: Up to 64 Kbytes
ï¯ SRAM1: Up to 32 Kbytes
ï¯ SRAM2: Up to 32 Kbytes
External Bus Interface
ï®Supports SRAM, NOR, NAND Flash, and SDRAM device
ï®Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
ï®8-/16-bit Data width
ï®Up to 25-bit Address bit
ï®Supports Address/Data multiplex
ï®Supports external RDY function
ï®Supports scramble function
ï¯ Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
ï¯ Possible to set two kinds of the scramble key
Note:
⢠It is necessary to prepare the dedicated software library
to use the scramble function.
USB Interface
USB interface is composed of Function and Host.
[USB function]
ï®USB2.0 Full-Speed supported
ï®Max 6 Endpoint supported
ï¯ Endpoint 0 is control transfer
ï¯ Endpoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
ï¯ Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
ï¯ Endpoint 1 to 5 comprise Double Buffer
ï¯ The size of each endpoint is according to the follows.
⢠Endpoint 0, 2 to 5: 64 bytes
⢠Endpoint 1: 256 bytes
Cypress Semiconductor Corporation
Document Number: 002-04864 Rev.*A
⢠198 Champion Court ⢠San Jose, CA 95134-1709
408-943-2600
Revised March 3, 2016
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