DS-72-34 Datasheet, PDF (16/18 Pages) Cymbet Corporation – I2C Real-Time Clock/Calendar with Integrated Backup Power

Preliminary
CBC34803 EnerChip™ RTC
GUIDELINES FOR IN-CIRCUIT TESTING OF THE INTERNAL ENERCHIP BATTERY
It is very important to verify EnerChip device connectivity after reflow solder process. It is important to read
and understand the proper test flow for the EnerChip devices. Following the proper test method will ensure
reworkability of boards.
Precautions and Important Processes
After assembly on a printed circuit board, the CBC34803 integrated solid state battery is in an uncharged
state. It is important that the CBC34803 battery remain untested and uncharged until the last step of an in-
circuit system test so that if other components fail test and need to be replaced, the CBC34803 will still be in a
reflow-solderable state. The crystal and RTC in the CBC34803 can be tested independently from the battery at
the same time the other system elements are being tested.
There are two considerations when doing post-assembly testing of the user’s circuit board:
1. When performing circuit testing, short the internal EnerChip battery to GND by forcing the VCHG/VEC pins
to ground potential during testing of the EnerChip RTC and other circuit functions. This will prevent the
integrated EnerChip from accumulating charge while the CBC34803 VDD and EN pins are active.
2. When the overall circuit testing is complete, it is permissible to verify connection to the EnerChip battery
and 4.1V output of the charge pump at the VCHG pin by forcing the CBC34803 VDD and EN pins high for
NO MORE THAN 3 SECONDS. Activating the charge pump for longer than 3 seconds will put sufficient
charge into the EnerChip that board level rework is no longer permitted without destroying the EnerChip.
Factory In-Circuit EnerChip Post Assembly Test Steps
CBC34803 In-Circuit Test Procedure
1. In order to keep the CBC34803 battery from charging during testing, apply GND using an in-circuit test bed
pin or other shorting method to the VCHG and VEC pins (6 and 7, respectively) that are normally tied to-
gether on the PCB. Alternatively, the EN pin on the CBC34803 can be forced to a logic low before perform-
ing board level testing as this will also prevent charge from accumulating in the battery. WARNING: If the
enable pin is asserted for more than 3 seconds with VDD ≥ 2.5 volts, the CBC34803 may not be reflowed
again.
2. Enable power domains under test, with VCHG/VEC net shorted to GND or EN forced to a logic low level.
3. Run all vectors to ensure proper functionality of all semiconductor devices.
4. After all other circuits are functional and boards have been reworked if needed.
5. Apply voltage to VIN that is in the range of 2.5V to 5.5V. (Note: VIN = VDD.)
6. Verify that the VCHG/VEC net is 4.1 volts +/- 0.025 volts.
7. Allow the battery to charge a very small amount by leaving the device in the above-noted configuration for
one second.
8. The chart in Figure 7 should be referenced to determine the voltage on the VCHG/VEC pin to be expected
after driving the ENABLE pin high for one second. The decay curves in the chart represent specific load
impedances as might be encountered with Automated Test Equipment (ATE). Additionally, the decay curves
represent the span of EnerChip cell impedances as specified in the respective data sheets. Note: If not
using ATE with the ability to add a load impedance, it will be necessary to add resistance in parallel with
the voltage measurement device so the readings will match the graph of Figure 7. Any measurement
equipment and associated impedance circuits must only be temporally tied to the VCHG/VEC node for
the time needed to make the measurement (seconds) and no longer as the measurement impedance
will cause the battery to become discharged below 2.5V at which time the cell will become permanently
damaged.
9. The graph in Figure 7 depicts the time-dependent and temperature-dependent voltage of the EnerChip RTC
after applying a 4.1VDC charging voltage for approximately one second, followed by a brief discharge at
a specific load resistance. Using this graph as a guide, the test engineer can develop a simple test that is
feasible with the available test equipment and fixtures and meets the production throughput needs.
©2014-2015 Cymbet Corporation • Tel: [phone] • www.cymbet.com
DS-72-34 V.20

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