DS-72-34 Datasheet, PDF (11/18 Pages) Cymbet Corporation – I2C Real-Time Clock/Calendar with Integrated Backup Power

Preliminary
CBC34803 EnerChip™ RTC
Crystal Oscillator Selection
The CBC34803 should work with any standard 32.768kHz tuning fork crystal with a load capacitance rating
from 0 - 12.5pF and an ESR from 0 – 90kohms. Recommendations are as follows:
• Crystal load capacitance rating: 0 - 12.5pF
• Crystal ESR rating: 0 – 90kohms max
• No additional loading capacitors on the board
• Stray PCB capacitance on XO/XI: 2pF or less (less is better)
Typically, an oscillator allowance (OA) of 260-290kohms is generated. Increasing the loading capacitance on
the XI/XO pins will decrease the OA and using crystals with a higher ESR will reduce the OA margin. The crystal
will not affect the internal RTC current because a fixed bias current to the crystal is used. No external load
capacitance is required because the frequency offset from the crystal is digitally calibrated out, to within +/-
2ppm. Mainstream crystals (3.2mm x 1.5mm) generally have a maximum ESR rating of 70kohms. The smaller
2.0mm x 1.2mm crystals generally have a maximum ESR of 90kohms. Some crystal vendors, such as Epson
or Micro Crystal, might have some of the smaller crystals with lower ESR. Below is a list of crystals from several
vendors that have been tested:
Abracon: ABS07-32.768KHZ-7-T, ABS06-32.768KHZ-9-T, ABS25.32.768KHZ-T
Epson: FC-135, FC-12D, FC-12M
Micro Crystal: CC7V-T1A, CM7V-T1A
Required Calibration of Crystal Oscillator Frequency for Proper System Operation
The CBC34803 uses an ultra-low power Real Time Clock chip that differs slightly in operation from legacy
higher power real time clocks. The following instructions must be implemented for proper operation.
In order to reduce power to the lowest level possible, the input load capacitance on the XO and XI pins on the
CBC34803 device has been purposely designed to be as low as possible and still retain good stability and
startup characteristics. Consequently the crystal oscillator frequency on CBC34803 parts will tend to run
100-300ppm higher in frequency than the nominal value of 32.768KHz when used with a 5 to 12pF crystal.
In order to compensate for this higher frequency, the CBC348o3 device has a set of calibration registers into
which the frequency offset in ppm is written. The clock divider chain then adds or subtracts pulses based
on the value in the calibration registers to insure that the nominal divided clock frequencies are now at
submultiples of 32.768Khz.
When calibrating the CBC34803, the fundamental crystal frequency is not changed, only the frequencies that
are below the fundamental frequency are modified by writing the ppm offset coefficients into the calibration
registers. This can be verified by setting the FOUT function to be a square wave and then measuring the various
undivided clock output vs. the divided clock after calibration. Please refer to the Ambiq Micro datasheet for the
calibration procedure.
Depending on the desired frequency tolerance for the application, one of two approaches can be used for
calibration:
1. For those applications where it is cost prohibitive to calibrate each unit, a generic calibration offset
can be used. The resulting frequency deviation will then match the crystal tolerance. Typically during
system qualification testing, several units will be tested and an average of all the fundamental oscillator
frequencies will be used to calculate the ppm offset coefficient to be written into the calibration registers.
2. For those applications requiring high precision, each unit can be measured and calibrated before shipping.
This approach will yield a system with a minimum of 2ppm frequency tolerance.
©2014-2015 Cymbet Corporation • Tel: [phone] • www.cymbet.com
DS-72-34 V.20

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