SM3 Datasheet, PDF (26/36 Pages) Connor-Winfield Corporation – ULTRA MINIATURE STRATUM 3 MODULE

Application Notes continued
Master/Slave Configuration – A pair of devices are interconnected by cross-coupling their respective M/S Outputs or Output1 to
the other device’s M/S REF input (See Figure 8). Additionally, the reference inputs for each device would typically be correspondingly the
same, so that when a Master/Slave switch occurs, synchronization would continue with the same reference. (The SM3 continues to
qualify the reference inputs even in slave mode.) The references may be driven by the same signal directly or via separate drivers, as the
redundancy of that part of the system requires. Distribution path lengths are not critical here, as a phase build-out will occur when a
device switches from slave to master.
The path lengths of the two M/S Output to M/S REF signals is of interest, however. They need not be the same. However, to
accommodate path length delays, the SM3 provides a programmable phase skew feature, which allows the application to offset the
output clock from the cross-reference signal by -32ns to +31.75ns. This offset may therefore be programmed to exactly compensate for
the actual path length delay associated with the particular application’s cross-reference traces. The offset may be further adjusted to
accommodate any output clock distribution path delay differences. Phase offset is programmed by writing to the Phase_Offset register,
and is typically a one-time device initialization function. (See register description and Register Access Control sections). Thus, master/
slave switches with the SM3 devices may be accomplished with near-zero phase hits.
Master/Slave Operation and Control – The Master/Slave state is always manually controlled by the application. Master or slave
state of a device is determined by the MASTER SELECT pin. Choosing the master/slave states is a function of the application, based on
the configuration of the rest of the system and potential detected fault conditions.
M/S REF input activity and frequency may be monitored by reading the M/S_Activity register (0x07). Any changes on M/S REF input
are signaled by the SPI_INT and noted by reading the Intr_Event register (0x12) bits 2 & 3.
When operating in Register Access Manual Control mode, it is important to set the slave reference selection the same as the master
to ensure use of the same reference when/if the slave becomes master. In Register Access Manual Control mode, the Ref_Mask
register should also be written to the same value for both devices.
Master/slave switches should be performed with minimal delay between switching the states of each of the two devices. This can be
easily accomplished, for example, by controlling the master/slave state with a single signal, coupled to one of the devices through an
inverter. While performing Master/Slave switches, one has to make sure that both modules are not in slave mode. This creates a “Timing
Loop” that can cause undesirable effects.
In the case of Register Access Automatic Control mode, where reference selection is automatic, it is necessary to read the
operational mode BITS 3-0) from the master’s Op_Mode register and write it to the slave’s Op_Mode register. The master’s reference
selection will then be used by the slave when it becomes master. In addition to having the references populated the same, and in the
same order for both devices, it is desireable to write the reference frequency and priority registers Ref(1-4)_Frq_Priority and the
Ref_Mask registers to the same values for both devices to ensure seamless master/slave switches.
Reset – Device reset is an initialization time function, which resets internal logic and register values. A reset is performed
automatically when the device is powered up. Registers return to their default values, as noted in the register descriptions.
Holdover History Accumulation and Maintenance -- Holdover history accumulation and maintenance may be controlled in greater
detail if register bus access to the device is provided. Holdover history accumulation and control encompasses three device internal
registers, three bus access registers for control and access, and two status bits in the DPLL_Status register.
Hold Over History
Accumulation Register
Active
Hold Over History
Backup
Hold Over History
Once lock has been achieved, holdover history is compiled in the accumulation register. It is transferred to the Active holdover history
when it is ready (typically in about 15 minutes). The “Holdover Available” bit and output pin are set to “1”. From then on, the Active
holdover history is continually updated and kept in sync with the holdover history accumulation register. (See Figure 11).
Data Sheet #: TM052 Page 26 of 36 Rev: 03 Date: 11/07/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice