FX629 Datasheet, PDF (5/10 Pages) CML Microcircuits – Delta Modulation Codec

Codec Timing Information
ENCODER TIMING
ENCODER
CLOCK
t CH
DATA CLOCKED
ENCODER DATA
OUTPUT
t _PCO
DECODER TIMING
DECODER
CLOCK
t CL
t _IF
DATA CLOCKED
t CH
t IR
DECODER DATA
INPUT
t _SU
MULTIPLEXING FUNCTION
ENCODER
OUTPUT
HIGH Z
t _DR
DATA ENABLE
t_H
DATA TRUE TIME
HIGH Z
t _DF
TIMING
t_CH Clock '1' Pulse Width
1.0µs Min.
t_IR Clock Rise Time
100ns Typ.
t_CL Clock '0' Pulse Width
1.0µs Min.
t_IF Clock Fall Time
100ns Typ.
t_DR Data Rise Time
100ns Typ.
Fig.4 Codec Timing Diagrams
t_SU Data Set-up Time
450ns Min.
t_H Data Hold Time
600ns Min.
t_DF Data Fall Time
100ns Typ.
t_SU + t_H = Data True Time
t_PCO Clock to Output Delay Time
750ns Max.
Xtal Input Frequency
1.024MHz.
Digital to Analogue Performance ...... Using the bit sequence tests shown in Table 1 (below) at the
Decoder Input pin, the analogue signals measured at the Decoder Output pin are 800Hz ± 10Hz at the levels
described.
Sample Rate
16kbit/s
32kbit/s
Bit Sequence at Decoder Input
11011011010010010010
1101101101010100100100100100101010110110
“Run of Threes” Output Level
(%)
(dBm0)
0
-29.2 ± 2
0
-30.0 ± 2
16kbit/s
11111011010000010010
30
32kbits
1111110110101010000100000010010101011110
30
Table 1 Bit Sequence Tests and Results
5
0±1
0±1
at 800Hz