FX629 Datasheet, PDF (3/10 Pages) CML Microcircuits – Delta Modulation Codec

Pin Number Function
FX629J
12
No connection
13
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.
14
No connection
15
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non-
operational state. When at a logical '1' the codec operates normally. Internal 1M Ω Pullup.
16
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to V_DD/2. When this pin is at a logical '1' the
decoder operates as normal. Internal 1MΩ Pullup.
17
Decoder Input : The received digital signal input. Internal 1MΩ Pullup.
18
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.
19
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.
20
Clock Mode 2 :
Clock Mode 1 Clock Mode 2 Facility
21
Clock Mode 1 :
0
0
External clocks
Internal 1MΩ
0
1
Internal, 64kb/s = f ÷ 16
Pullups.
1
0
Internal, 32kb/s = f ÷ 32
1
1
Internal, 16kb/s = f ÷ 64
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock
frequencies are available at the ports for external circuit synchronization.
Independent or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode. Optimum performance will be achieved when the
applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of
128kHz.
22
V_DD : Positive Supply. A single + 5 volt power supply is required.
3