FX629 Datasheet, PDF (4/10 Pages) CML Microcircuits – Delta Modulation Codec

Codec Integration
FX629 PARAMETERS
MEASURED HERE
REGULATED POWER
SUPPLY
FX629 PARAMETERS
MEASURED HERE
SYSTEM
INPUT
ANALOGUE
INPUT
INTERFACE
(BALUN
&
BUFFER)
FX629
ENCODER
FX629
DECODER
DATA
CLOCKS
CLOCK MODE ^DATA
16/32/64kb/s
CLOCKS
1.024 MHz
SYNCHRONOUS CLOCK
AND
DATA SYSTEM
1.024 MHz
ANALOGUE
OUTPUT
INTERFACE
(BALUN
&
BUFFER)
SYSTEM
OUTPUT
Fig.2 System Configuration Diagram – showing the FX629, which with the indicated interfacing, will conform to
the Mil-Std-188-113 Specification
Component
Unit Value
Note – with reference to Figure 3 (below)
R₁
1M
R₂
Selectable
C₁
33p
C₂
33p
C₃
1.0µ
C₄
1.0µ
C₅
1.0µ
X₁
1.024 MHz
Tolerance :– Resistors ± 10%
Oscillator Inverter bias resistor.
Xtal Drive limiting resistor.
Xtal Circuit drain capacitor.
Xtal Circuit gate capacitor.
Encoder Input coupling capacitor – The drive source impedance to this
input should be less than 100Ω. Output Idle channel noise levels will
improve with an even lower source impedance.
Bias decoupling capacitor.
V_DD decoupling capacitor.
A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock
rates. Xtal circuitry shown is in accordance with CML application note
D/XT/1 April 1986.
Capacitors ± 20%
V_DD
XTAL/CLOCK
X₁
C₂
C₁
R₂
1
R₁
XTAL
2
N/C
3
VDD
22
CLOCK MODE 1
21
CLOCK MODE 2
20
ENCODER DATA CLOCK
4
ALGORITHM
19
ENCODER OUTPUT
5
DECODER DATA CLOCK
18
ENCODER FORCE IDLE
6
FX629J
DECODER INPUT
17
C₅
DATA ENABLE
7
DECODER FORCE IDLE
16
N/C
8
BIAS
9
ENCODER INPUT
10
C₃
11
C₄
V_SS
POWERSAVE
15
N/C
14
DECODER OUTPUT
13
N/C
12
Fig.3 Recommended External Components
VSS
4