FX929B Datasheet, PDF (29/48 Pages) CML Microcircuits – Flexible Operating Modes

4-Level FSK Modem Data Pump
FX929B
CRC2
This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block. It is calculated by the
modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block
using the generator polynomial:
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
Notes:
In receive mode the CRC2 checksum circuits are initialised on completion of any task other than NULL
or RILB. In transmit mode the CRC2 checksum circuits are initialised on completion of any task other
than NULL, TIB or TLB.
Command Register bit B5 (CRC) allows the user to select between two different forms of the CRC0,
CRC1 and CRC2 checksums. When this bit is set to '1' the CRC generators are initialised to 'all
zeros', as required by RD-LAP systems. When this bit is set to '0' the CRC generators are initialised
to 'all ones' as required by CCITT X25 based systems. It should always be set to '1' for RD-LAP
compatibility, other systems may set this bit as required.
Forward Error Correction
In transmit mode, the FX929B uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header',
'Intermediate' or 'Last' Block or the 30 bits of a Station ID Block into a 66 or 22-symbol sequence which
includes FEC information.
In receive mode, the FX929B decodes the received 22 or 66 symbols of a block into 30 or 96 bits of binary
data using a 'Soft Decision' Viterbi algorithm to perform decoding and error correction.
Interleaving
The 66 symbols of a 'Header', 'Intermediate' or 'Last' block are interleaved by the modem before transmission
(and before the 'S' symbols are added) to give protection against the effects of noise bursts and short fades.
The 22 symbols of a 'Station ID' Block are not interleaved.
In receive mode, the FX929B de-interleaves the received symbols after stripping out the 'S' symbols and prior
to decoding.
1.5.7 Transmitted Symbol Shape
Bit 4 of the Command Register (TXIMP) affects the transmit baseband signal and the receive signal
equalisation as follows.
If the TXIMP bit is '0', then the transmit baseband signal is generated by feeding full-width 4-level symbols into
the RRC lowpass filter, and the receive signal equalisation is optimised for this type of signal. With this setting
the FX929B is compatible with FX929A devices.
If the TXIMP bit is set to '1', then impulses, rather than full-width symbols, are fed into the RRC filter when in
Tx mode, and the receive signal equalisation is suitably adjusted in Rx mode.
© 1997 Consumer Microcircuits Limited
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D/929B/1