FX929B Datasheet, PDF (27/48 Pages) CML Microcircuits – Flexible Operating Modes

4-Level FSK Modem Data Pump
FX929B
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID or R4S task is
written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the
Command Register or by changing the TXRXN or PSAVE bits of the Mode Register.
In transmit mode this bit is '0'.
Status Register B3: CRCERR - CRC Checksum Error
In receive mode this bit will be updated at the end of a SFP, RHB, RILB or RSID task to reflect the result of
the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error. In transmit
mode this bit will be '0'.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task, or by changing the TXRXN or PSAVE bits of the Mode Register.
Status Register B2: SRDY - 'S' Symbol Ready
In receive mode, this bit is set to '1' whenever an 'S' symbol has been received. The µC may then read the
value of the symbol from the SVAL field of the Status Register. In transmit mode, this bit is set to '1' whenever
an 'S' symbol has been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
TXRXN or PSAVE bits of the Mode Register.
Status Register B1, B0: SVAL - Received 'S' Symbol Value
In receive mode, these two bits reflect the value of the latest received 'S' symbol. In transmit mode, these two
bits will be '0'.
1.5.5.6 Data Quality Register
In receive mode, the FX929B continually measures the 'quality' of the received signal, by comparing the actual
received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level FSK
baseband signal.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 14 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
© 1997 Consumer Microcircuits Limited
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D/929B/1