FX929B Datasheet, PDF (28/48 Pages) CML Microcircuits – Flexible Operating Modes

4-Level FSK Modem Data Pump
FX929B
250
200
150
DQ
100
50
0
8
9
10
11
12
13
14
15
16
S/N dB (Noise in 2 x Symbol Rate Bandwidth)
Figure 14 Typical Data Quality Readingvs S/N
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing
lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when
the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to 'Wide'
or if the received signal waveform is distorted in any significant way.
Section 1.6.6 describes how monitoring the Data Quality reading can help improve the overall system
performance in some applications.
1.5.6 CRC, FEC and Interleaving
Cyclic Redundancy Codes
CRC0
This is a six-bit CRC check code used in the Station ID Block. It is calculated by the modem from the first 24
bits of the block ( Bytes 0,1 & 2) as follows:
The 24 bits are considered as the coefficients of a polynomial M(x) of degree 23, such that the msb bit (7) of
byte 0 is the coefficient of x23, and bit 0 of byte 2 is the coefficient of x0.
The polynomial F(x) of degree 5 is calculated as being the remainder of the modulo-2 division
x6M(x) / (x6 + x4 + x3 + 1 )
The polynomial x5 + x4 + x3 + x2 + x1 + x0 is added (modulo-2) to F(x)
The coefficients of F(x) are placed in the 6-bit CRC0 field, such that the coefficient of x5 corresponds to the
msb of CRC0.
CRC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block. It is calculated by the
modem from the first 80 bits of the block ( Bytes 0 to 9 inclusive) using the generator polynomial:
x16 + x12 + x5 + 1
© 1997 Consumer Microcircuits Limited
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D/929B/1