FX919B Datasheet, PDF(25/47 Page) CML Microcircuits – Excellent Radio Fading Performance

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FX919B Datasheet, PDF (25/47 Pages) CML Microcircuits – Excellent Radio Fading Performance

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4-Level FSK Modem Data Pump

Mode Register B6: INVSYM - Invert Symbols

This bit controls the polarity of the transmitted and received symbol voltages.

FX919B

B6 Symbol

'+3'

'-3'

'+3'

'-3'

Signal at TXOP

Above VBIAS

Below VBIAS

Above VBIAS

Signal at RXFB

Below VBIAS

Above VBIAS

Below VBIAS

Mode Register B5: TXRXN - Tx/Rx Mode

Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode.

Note that changing between receive and transmit modes will cancel any current task.

Mode Register B4: RXEYE - Show Rx Eye

This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the modem

into a special test mode, in which the input of the Tx o/p buffer is connected to the Rx Symbol/Clock extraction

circuit at a point which carries the equalised receive signal. This may be monitored with an oscilloscope (at the

TXOP pin itself), to assess the quality of the complete radio channel including the Tx and Rx modem filters, the

Tx modulator and the Rx IF filters and FM demodulator.

The resulting eye diagram (for reasonably random data) should ideally be as shown in the following Figure 13,

with 4 'crisp' and equally spaced crossing points.

Figure 13 Ideal 'RXEYE' Signal

Mode Register B3: PSAVE - Powersave

When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx Symbol &

Clock extraction circuits and the Tx o/p buffer will be disabled, and the TxOp pin will be connected to VBIAS

through a high value resistance. The Xtal Clock oscillator, Rx i/p amplifier and the ÂµC interface logic will

continue to operate.

Setting the PSAVE bit to '0' restores power to all of the chip circuitry. Note that the internal filters - and hence

the TxOp pin in transmit mode - will take about 20 symbol-times to settle after the PSAVE bit is taken from '1' to

'0'.

Mode Register B2, B1, B0

These bits should be set to '000'.

D/919B/1

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