FX919B Datasheet, PDF (24/47 Pages) CML Microcircuits – Excellent Radio Fading Performance

4-Level FSK Modem Data Pump
FX919B
The DOC capacitors are isolated form the charging and discharging circuits in ‘Hold mode, allowing the
voltages to float.
Control Register B1, B0: PLLBW - Phase-Locked Loop Modes
These two bits have no effect in transmit mode. In receive mode, they set the 'normal' bandwidth of the Rx
clock extraction Phase Locked Loop circuit. This setting will be temporarily overridden by the automatic
sequencing of an AQSC command.
B1 B0
00
01
10
11
PLL Mode
Hold
Narrow Bandwidth
Medium Bandwidth
Wide Bandwidth
The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the
frequency of the receiving modem's Xtal are both within ±100ppm of nominal, except at the start of a symbol
clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in section 1.6.3.
If the received symbol rate and Xtal frequency are both within ±20ppm of nominal then selection of the 'Narrow
Bandwidth' setting will give better performance, especially through fades or noise bursts which might otherwise
pull the PLL away from its optimum timing, but in this case it is recommended that the PLLBW bits are only set
to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth' mode for about 200 symbol
times.
The 'Hold' setting disables the feedback loop of the PLL, which continues to run at a rate determined only by
the actual Xtal frequency and the setting of the Control Register CKDIV bits.
1.5.5.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register B7: IRQNEN - IRQN Output Enable
When this bit is set to '1', the IRQN chip output pin is pulled low (to Vss) whenever the IRQ bit of the Status
Register is a '1'.
© 1997 Consumer Microcircuits Limited
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D/919B/1