DB829 Datasheet, PDF (15/29 Pages) CML Microcircuits – Low Voltage Operation

Baseband Signal Processor
15
MX829 PRELIMINARY INFORMATION
5.3.2 RXDATA Register (Hex address $42)
This register contains the last byte of data received. It is updated every 8 bits at the same time as the RXSUMF bit in the
STATUS register is updated.
The RXDATA register is double buffered, thus giving the user up to 8 bit periods to read the data before it is overwritten by
the next byte.
5.4 MSK Checksum Generation and Checking
5.4.1 Generation
The checksum generator takes the m x 8 bits from the m bytes of information, sequentially loaded into the TXDATA
register and divides them modulo-2, by the generating polynomial:
X15 + X14 + X13 + X11 + X4 + X2 + 1
It then takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an EVEN parity bit
generated from the initial m x 8 bits and the 15-bit remainder (with the last bit inverted).
This 16-bit word is used as the "CHECKSUM". See Figure 5.
(m = the number of bytes in the information to be sent)
m x 8 bits
÷ polynomial
15-bit remainder
invert last bit
m x 8 bits
15-bit
remainder
P
"CHECKSUM"
Figure 5: Checksum Generation
EVEN parity on
whole Tx frame
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