DB829 Datasheet, PDF (14/29 Pages) CML Microcircuits – Low Voltage Operation

Baseband Signal Processor
14
MX829 PRELIMINARY INFORMATION
5.2.8 RX SYNC WORD Register (Hex $44)
This is a two byte register that defines the 16-bit programmable synchronization word. This word is compared with the
incoming Rx data and, if a match is found, it is indicated in the STATUS register and an interrupt is generated. Bit 15, the
MSB of the first byte, is loaded first.
8-bit Read Only Registers
HEX
ADDRESS/
COMMAND
$41
$42
REGISTER BIT 7
NAME
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
STATUS
RXDATA
0 RXSUMF TXIDLEF RXDATAF TXDATAF RX SYNC SYNTF SYNCF
WORDF
<----------------------------------------------- RXDATA ----------------------------------------------->
BIT 7 BIT 6
BIT 5
BIT 4
BIT 3
BIT 2 BIT 1 BIT 0
5.3 Read Only Register Description
5.3.1 STATUS Register (Hex address $41)
This register is used to indicate the status of the device as described below:
Note: After reading the contents of the Status Register, all bits in the Status Register are reset to a zero state and the
IRQ, externally generated by the MX829, is cleared.
Bit 7
RXSUMF
(Bit 6)
TXIDLEF
(Bit 5)
RXDATAF
(Bit 4)
TXDATAF
(Bit 3)
RX SYNC
WORDF
(Bit 2)
SYNTF
(Bit 1)
SYNCF
(Bit 0)
Not used, always set to zero.
When this bit is "1", the Rx checksum is correct.
When this bit is "0", the Rx checksum is incorrect.
This bit is updated and latched in, after reception of every eight bits (see section 5.2.3).
When all the Tx data and any checksum and one "hang-bit" have been transmitted, this bit will be set to "1"
to indicate that the transmitter is idle. This bit is reset to "0" immediately after reading the STATUS register.
When this bit is set to "1", an interrupt may be generated depending on the state of the TXIDLEM bit in the
CONTROL 3 / IRQ ENABLE register.
When a full byte of data is received and is available in the RXDATA register, this bit will be set to "1". This bit
is reset to "0" immediately after reading the STATUS register. When this bit is set to "1" an interrupt may be
generated depending on the state of the RXDATAM bit in the CONTROL 3 / IRQ ENABLE register.
When the Tx data buffer is empty this bit will be set to "1".
This bit is reset to "0" immediately after reading the STATUS register. When this bit is set to "1", an interrupt
may be generated depending on the state of the TXDATAM bit in the CONTROL 3 / IRQ ENABLE register.
This bit is only defined when RX SYNC WORD PRIME is enabled.
When the data sequence specified in the RX SYNC WORD register has been successfully matched to the
Rx incoming data, this bit will be set to "1".
This bit is reset to "0" immediately after reading the STATUS register. When this bit is set to "1", an interrupt
will be generated, the checksum generator and byte counter will be reset and SYNC PRIME, SYNT PRIME
and RX SYNC WORD PRIME will be reset.
This bit is only defined when SYNT PRIME is enabled.
When the data sequence specified by SYNT has been successfully matched to the Rx incoming data, this bit
will be set to "1".
This bit is reset to "0" immediately after reading the STATUS register. When this bit is set to "1", an interrupt
will be generated, the checksum generator and byte counter will be reset and SYNC PRIME, SYNT PRIME
and RX SYNC WORD PRIME will be reset.
This bit is only defined when SYNC PRIME is enabled.
When the data sequence specified by SYNC has been successfully matched to the Rx incoming data, this
bit will be set to "1".
This bit is reset to "0" immediately after reading the STATUS register. When this bit is set to "1", an interrupt
will be generated, the checksum generator and byte counter will be reset and SYNC PRIME, SYNT PRIME
and RX SYNC WORD PRIME will be reset.
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