M-8880 Datasheet, PDF (5/13 Pages) Clare, Inc. – M-8880 DTMF Transceiver

M-8880
Table 4 Control Register A Description
Bit
Name
Function
Description
b0
TOUT
Tone output A logic 1 enables the tone output. This function can be implemented in either the burst mode or
nonburst mode.
b1 CP/DTMF Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When
the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow
call progress tones to be detected. Call progress tones within the specified bandwidth will be pre-
sented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also,
when the CP mode and burst mode have both been selected, the transmitter will issue DTMF sig-
nals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained
from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode has been selected.
b2
IRQ
Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been se-
lected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal
has been received and has been present for the guard time or (2) the transmitter is ready for more
data (burst mode only).
b3
RSET Register select A logic 1 selects control register B on the next write cycle to the control register address. Subse-
quent write cycles to the control register are directed back to control register A.
Table 5 Control Register B Description
Bit
Name
Function
Description
b0
BURST
Burst mode A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired
DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific
duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately fol-
lowing the pause, the status register is updated indicating that the transmit data register is ready
for further instructions, and an interrupt will be generated if the interrupt mode has been enabled.
Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed
by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired dura-
tion may be generated.
b1
TEST
Test mode By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted)
signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output
waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented.
b2
S/D
Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), ei-
generation ther now or column tones (low or high group) can be generated depending on the state of b3 in
control register B.
b3
C/R
Column/row When used in conjunction with b2 (above), the transmitter can be made to generate single-row or
tones
single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column fre-
quencies.
V_L and V_H correspond to the low-group and high-group ampli-
tude, respectively, and V²_IMD is the sum of all the intermodulation
components. The internal switched capacitor filter following the
D/A converter keeps distortion products down to a very low
level.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. A number of
M-8880 devices can be connected as shown in Figure 8 using
only one crystal.
Microprocessor Interface
The M-8880 uses a microprocessor interface that allows pre-
cise control of transmitter and receiver functions. Five internal
registers are associated with the microprocessor interface,
which can be subdivided into three categories: data transfer,
transceiver control, and transceiver status. Two registers are
associated with data transfer operations. The receive data,
read-only, contains the output code of the last valid DTMF tone
pair to be decoded. The data entered in the transmit data regis-
ter determines which tone pair is to be generated (see Table 2).
Figure 8 Common Crystal Connection
Data can only be written to the transmit data register. Trans-
ceiver control is accomplished with two control registers (CRA
and CRB), occupying the same address space. A write opera-
tion to CRB can be executed by setting the appropriate bit in
CRA. The following write operation to the same address will
then be directed to CRB, and subsequent write cycles will then
be redirected to CRA. Internal reset circuitry clears the control
40-406-00012, Rev. G
Page 5
www.clare.com