CPC7581_1 Datasheet, PDF (11/17 Pages) Clare, Inc. – Line Card Access Switch

CPC7581
2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
State IN_RINGING Latch
Ringing
1
Make-
Before-
0
0
Break
Talk
0
Ringing
T_SD
Timing
Break Return
Switches Switch
(SW3)
-
Off
On
SW4 waiting for next zero-current crossing to
turn off. Maximum time is one-half of the ringing
Z cycle. In this transition state, current that is
On
Off
limited to the dc break switch current limit value
will be sourced from the ring node of the SLIC.
Zero-cross current has occurred
On
Off
Ringing
Switch
(SW4)
On
On
Off
To use break-before-make ringing switch release
timing, assert T_SD during ringing. This causes the
operational sequence shown in “Break-Before-Make
Operation Logic Table (Ringing to Talk Transition)” on
page 11 to occur.
2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
State IN_RINGING Latch
Ringing
1
All-off
1
0
All-off
1
Talk
0
Ringing
T_SD
Timing
Break Return
Switches Switch
(SW3)
Z
-
Off
On
Hold this state for one-half of the ringing cycle.
0 ^{SW4 waiting for zero current to turn off.}
Off
Off
Zero current has occurred. SW4 has opened
Off
Off
Z
Release break switches
On
Off
Ringing
Switch
(SW4)
On
On
Off
Off
Logic states and explanations are given in “Truth Table”
on page 9.
affected by the LATCH input and the T_SD input will
override state control.
2.3 Data Latch
The CPC7581 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10
(IN_RINGING), while the output of the data latch is an
internal node used for state control. When the LATCH
control pin is at logic 0, the data latch is transparent
and data control signals flow directly through to state
control. A change in input will be reflected in a change
is switch state. When the LATCH control pin is at logic
1, the data latch is active and a change in input control
will not affect switch state. The switches will remain in
the position they were in when the LATCH changed
from logic 0 to logic 1 and will not respond to changes
in input as long as the latch is at logic 1. The T_SD input
is not tied to the data latch. Therefore, T_SD is not
2.4 T_SD
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 8
(T_SD) will read a nominal 0 V. Normal output of T_SD is
typically equal to V_DD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown will activate forcing the switches to the all-off
state. At this point the current measured through the
break switches (SW1 and SW2) will drop to zero.
Once the device enters thermal shutdown it will
remain in the all-off state until the temperature of the
device drops below the de-activation level of the
thermal shutdown circuit. This permits the device to
R05
www.clare.com
11