CDB5345 Datasheet, PDF (8/27 Pages) Cirrus Logic – Evaluation Board for CS5345

CDB5345
3.2 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS5345, CS8406,
and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or byte-
wise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired hex value
can be typed directly in the register address box in the register map.
Figure 2. Register Maps Tab
3.3 Pre-Configured Script Files
Pre-configured script files are provided with the CDB5345 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 3.3.1 - 3.3.2.
3.3.1 Oscillator Clock - ADC Ch 1 In to In to SPDIF & PGA Out
Using the pre-configured script file named “Oscillator Clock - ADC Ch 1 In to SPDIF & PGA Out.txt”, an an-
alog input signal applied to channel 1 of the CS5345 input multiplexer will be digitized by the ADC, transmit-
ted in S/PDIF format by the CS8406, and will be output through the active output filter and RCA jacks.
The canned oscillator is the source of MCLK. The CS5345 is the sub-clock master to the CS8406 and the
PCM1I/O header.
8
DS658DB1