CDB5345 Datasheet, PDF (12/27 Pages) Cirrus Logic – Evaluation Board for CS5345

CDB5345
5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
SUBCLK1
0
SUBCLK0
5.3.1 SUBCLOCK SOURCE (BITS 1:0)
Default = 01
Function:
This bit selects the source of the CS5345 SCLK and LRCK signals. Table 2 shows the available set-
tings.
Table 2. Subclock Source
SUBCLOCK1 SUBCLOCK
0
0
0
1
1
0
1
1
Subclock Source
- CS5345 is Master
- CS8406 is Slave to CS5345
- PCM I/O Header Subclocks are Output from CS5345
- CS5345 is Slave to CS8406
- CS8406 is Master
- PCM I/O Header Subclocks are Output from CS8406
- CS5345 is Slave to Header
- CS8406 is Slave to Header
- PCM I/O Header Subclocks are an Input
Reserved
5.4 TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H
7
Reserved
6
Reserved
5
Reserved
4
CS8406
3
Reserved
2
Reserved
1
Reserved
0
Reserved
5.4.1 CS8406 SDIN SOURCE (BIT 4)
Default = 0
Function:
These bit selects the source of the CS8406 SDIN signal. Table 3 shows the available settings.
Table 3. CS8406 SDIN Source
CS8406
0
1
CS8406 SDIN Source
Reserved
CS5345 SDOUT
12
DS658DB1