CDB5345 Datasheet, PDF (11/27 Pages) Cirrus Logic – Evaluation Board for CS5345

5. FPGA REGISTER DESCRIPTION
CDB5345
5.1 CODE REVISION ID - ADDRESS 01H
7
Rev7
6
Rev6
5
Rev5
4
Rev4
3
Rev3
2
Rev2
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
1
Rev1
0
Rev0
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
MCLK
5.2.1 MCLK SOURCE (BIT 0)
Default = 0
Function:
This bit selects the source of the CS5345 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK
0
1
MCLK Source
Canned Oscillator
M1 position on PCM1 I/O Header
DS658DB1
11