CS42L51 Datasheet, PDF (71/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
6.27 Status (Address 20h) (Read Only)
7
6
5
4
3
2
1
0
Reserved SP_CLKERR SPEA_OVFL SPEB_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: x
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 37 for valid clock ratios.
Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Signal Processing Engine Overflow (MIXX_OVFL)
Default: x
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: x
Function:
Indicates a digital overflow condition within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the
associated ADC’s.
6.28 Charge Pump Frequency (Address 21h)
7
6
5
4
CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ
3
2
1
0
3
Reserved
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
2
Reserved
1
Reserved
0
Reserved
N CHRG_FREQ[3:0] Frequency
0
0000
...
...
15
1111
6----4----x_---F_----s_-
N+2
Function:
Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs,
should the switching frequency interfere with other system frequencies such as those in the AM radio band.
Note: Distortion performance may be affected.
DS679A2
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