CS42L51 Datasheet, PDF (41/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
4.9 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby,
1. Mute the DAC’s & ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
fully muted sate.
3. Bring RESET low.
No Power
1. No audio signal
generated.
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Registers reset
to default.
RESET = Low? ^Yes
No
Control Port
Active
PDN bit = '1'b? ^Yes
No
No
Valid
MCLK Applied?
20 ms delay
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
Standby Mode
1. No audio signal generated.
2. Control Port Registers retain
settings.
No Control Port Valid Yes
Write Seq. within
10 ms?
ADC Initialization
2048 internal
MCLK cycle delay
Digital/Analog
Output Muted
DAC Initialization
50 ms delay
Charge Pump
Powered Up
Power Off Transition
1. Audible pops.
Hardware Mode
Minimal feature
set support.
Reset Transition
1. Pops suppressed.
ERROR: Power removed
Software Mode
Registers setup to
desired settings.
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
No
Valid
MCLK/LRCK
Ratio?
Yes
20 µs delay
Headphone Amp
Powered Up
RESET = Low
ERROR: MCLK/LRCK ratio change
Normal Operation
Audio signal generated per control port or stand-
alone settings.
PDN bit set to '1'b
(software mode only)
Headphone Amp
Powered Down
20 µs delay (DAC
only)
Stand-By
Transition
1. Pops suppressed.
ERROR: MCLK removed
Analog Output Freeze
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
Figure 23. Initialization Flow Chart
DS679A2
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