CS42L51 Datasheet, PDF (38/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

4.5.2
CS42L51
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In hardware mode the CODEC operates in single-speed only. In software mode the CODEC operates in
either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
4.5.3
MCLK
÷1
0
÷2
1
÷ 128
Double
Speed
00
÷ 128
Single
Speed
01
÷ 256
Half
Speed
10
÷ 512
Quarter
Speed
11
LRCK Output
(Equal to Fs)
SPEED[1:0]
MCLKDIV2
÷2
Double
Speed
00
÷2
Single
Speed
01
÷4
Half
Speed
10
÷8
Quarter
Speed
11
SCLK Output
Figure 18. Master Mode Timing
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters, without the need for ex-
ternal buffers. The 3ST_SP bit places the internal buffers for the serial port signals in a high-impedance
state, allowing another device to transmit clocks or data without bus contention.
CS42L51
Transmitting Device #1
SDOUT
Transmitting Device #2
3ST_SP
SCLK/LRCK
Receiving Device
Figure 19. Tri-State Serial Port
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