SA53 Datasheet, PDF (7/14 Pages) Cirrus Logic – Switching Amplifier

Product Innova tionFrom
SA53
I1, I2: Current sense pins. The SA53 supplies a positive current to these pins which is proportional to the current
flowing through the top side P-channel FET for that phase. Commutating currents flowing through the backbody
diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense
pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the
phase current that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If
the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of
this functionality are described in the applications section of this datasheet.
I_LIM/DIS1: This pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places OUT
1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit
latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND: This is the ground return connection for the V_DD logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it
is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.
Failure do to this may result in oscillations on the output pins during rising or falling edges.
V_DD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA53. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state
when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected.
TEMP: This logic level output goes high when the die temperature of the SA53 reaches approximately 135ºC. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC: These “no-connect” pins should be left unconnected.
2. SA53 OPERATION
The SA53 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two
high current outputs. The signal set of the SA53 is designed specifically to interface with a DSP or microcontroller.
A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault
signals provide important feedback to the system controller which can safely disable the output drivers in the pres-
ence of a fault condition. High side current monitors for both phases provide performance information which can be
used to regulate or limit torque.
SA53U