SA53 Datasheet, PDF (11/14 Pages) Cirrus Logic – Switching Amplifier

Product Innova tionFrom
SA53
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA53. Forward current in each top,
Pchannel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application configurations. The current
sense pins source current from the V_DD supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the
typical performance plot on page 4 of this data-
sheet.
Figure 7. Start-up Voltage and Current
NON-LIMITED MOTOR CURRENT
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
2.5 CYCLE-BY-CYCLE CURRENT
TIME
LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the mo-
tor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous
motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at
startup.
Because the output current of each upper output FET is measured, the SA53 is able to provide a very robust current
limit scheme. This enables the SA53 to safely and easily drive virtually any DC brush motor through a startup inrush
condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows start-
ing current and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal
(1t or 2t). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the
peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and I_LIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil-
lation.
This oscillation can be seen on the I_LIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t except when
commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the cur-
rent limit trips and the motor current reaches zero without a commutation edge which will typically reset the current
limit latch.
The current limit feature may be disabled by tying the I_LIM/Dis1 pin to GND. The current sense pins will continue to
provide top FET output current information.
SA53U
11