SA53 Datasheet, PDF (10/14 Pages) Cirrus Logic – Switching Amplifier

SA53
Product Innova tionFrom
2.1 LAYOUT CONSIDERATIONS
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as
ringing at the outputs.
The V_S supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the V_S
pins. Total inductance of the routing from the capacitor to the V_S and GND pins must be kept to a minimum to pre-
vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output
current should be placed near the SA53 as well. Capacitor types rated for switching applications are the only types
that should be considered.
The bypassing requirements of the V_DD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface
mount ceramic capacitor (X7R or NPO) connected directly to the V_DD pin is sufficient.
SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way
that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small
signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive
coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended.
2.2 FAULT INDICATIONS
In the case of either an over-temperature or short circuit fault, the SA53 will take no action to disable the outputs.
Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-
garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the
processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate
response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case,
the processor would recognize the condition as an external interrupt, which could be processed in software via an
Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the
disable inputs on the SA53.
Figure 6 shows an external SR flip-flop which provides a hard wired shutdown of all outputs in response to a fault in-
dication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condition
with a GPIO. This circuit can be used in safety critical
applications to remove software from the fault-shut-
Figure 6. External Fault Latch Circuit
down loop, or simply to reduce processor overhead.
In applications which may not have available GPIO,
PWM
the TEMP pin may be externally connected to the
adjacent DIS1 pin. If the device temperature reach-
SA53 ^SC
es ~135ºC all outputs will be disabled, de-energizing PROCESSOR
DIS2
TEMP
the motor. The SA53 will re-energize the motor when
the device temperature falls below approximately
95ºC. The TEMP pin hysteresis is wide to reduce the
GPIO
FAULT RESET
likelihood of thermal oscillations which can greatly
reduce the life of the device.
INTERRUPT
LATCHED FAULT
2.3 UNDER-VOLTAGE LOCKOUT
The undervoltage lockout condition results in the SA53 unilaterally disabling all output FETs until VS is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock- out
condition is in progress. The SA53 has two V_S connections: one for phase 1 and another for phase 2. The supply
voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis
on the UVLO circuit prevents oscillations with typical power supply variations.
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SA53U