CS2300-CP_09 Datasheet, PDF (7/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T_A = -10°C to +70°C (Commercial Grade);
C_L = 15 pF.
Parameters
Symbol
Conditions
Min Typ Max Units
Clock Input Frequency
Clock Input Pulse Width
Clock Skipping Timeout
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note 9)
f_{CLK_IN}
pw_{CLK_IN}
t_CS
f_{CLK_SKIP}
f_{CLK_OUT}
t_OD
t_OR
t_OF
t_JIT
t_LC
f_{CLK_IN} < 175 kHz
f_{CLK_IN} > 175 kHz
(Notes 4, 5)
(Note 5)
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note 6)
(Notes 6, 7)
(Notes 6, 8)
f_{CLK_IN} < 200 kHz
f_{CLK_IN} > 200 kHz
50 Hz -
140
-
10
-
20
-
50 Hz -
6
-
45
50
-
1.7
-
1.7
-
35
-
50
-
150
-
100
-
1
30 MHz
-
ns
-
ns
-
ms
80
kHz
75 MHz
55
%
3.0
ns
3.0
ns
- ps rms
- ps rms
- ps rms
200
UI
3
ms
Notes: 4.
5.
t_CS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t_CS.
Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 13 for more information.
6. f_{CLK_OUT} = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. 1 UI (unit interval) corresponds to t_{CLK_IN} or 1/f_{CLK_IN}.
DS843F1
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