CS2300-CP_09 Datasheet, PDF (14/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-CP
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2²³ LCO cycles (518 ms to
634 ms) after CLK_IN is removed (see Figure 10). This is true as long as CLK_IN does not glitch or have
an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a
change in frequency causing clock skipping and the 2²³ LCO cycle time-out to be bypassed and the PLL
to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2²³ LCO cycles pass,
the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Out-
put” on page 19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL
output will resume.
2²³ LCO cycles
2²³ LCO cycles
Lock Time
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
Figure 10. CLK_IN removed for > 2²³ LCO cycles
= invalid clocks
If it is expected that CLK_IN will be removed and then reapplied within 2²³ LCO cycles but later than t_CS,
the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in Figure 11;
note that the lower figure shows that the PLL output frequency may change and be incorrect without an
indication of an unlock condition.
tCS
2²³ LCO cycles
Lock Time
2²³ LCO cycles
tCS
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
CLK_IN
2²³ LCO cycles
tCS
Lock Time
ClkSkipEn= 1
ClkOutUnl=1
PLL_OUT
UNLOCK
= invalid clocks
Figure 11. CLK_IN removed for < 2²³ LCO cycles but > t_CS
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