CS2300-CP_09 Datasheet, PDF (27/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

8.6 Function Configuration 1 (Address 16h)
7
ClkSkipEn
6
AuxLockCfg
5
Reserved
4
EnDevCfg3
3
Reserved
2
Reserved
CS2300-CP
1
Reserved
0
Reserved
8.6.1
8.6.2
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
0
1
Application:
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 13
Note: f_{CLK_IN} must be < 80 kHz and re-applied within 20 ms to use this feature.
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 19
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.3
Enable Device Configuration Registers 3 (EnDevCfg3)
This bit, in conjunction with EnDevCfg1 and EnDevCfg2, configures the device for control port mode.
These EnDevDfg bits can be set in any order and at any time during the control port access sequence,
however they must all be set before normal operation can occur.
EnDevCfg3
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 20
Note: EnDevCfg1 and EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control
Port” on page 20.
DS843F1
27