CS2300-CP_09 Datasheet, PDF (28/32 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

8.7 Function Configuration 2 (Address 17h)
7
Reserved
6
Reserved
5
Reserved
4
ClkOutUnl
3
LFRatioCfg
2
Reserved
CS2300-CP
1
Reserved
0
Reserved
8.7.1
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 19
8.7.2
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the 32-bit User Defined Ratio.
LFRatioCfg
0
1
Application:
Ratio Bit Encoding Interpretation
20.12 - High Multiplier.
12.20 - High Accuracy.
“User Defined Ratio (RUD)” on page 16
8.8 Function Configuration 3 (Address 1Eh)
7
Reserved
6
ClkIn_BW2
5
ClkIn_BW1
4
ClkIn_BW0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
8.8.1
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
000
001
010
011
100
101
110
111
Application:
Minimum Loop Bandwidth
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
128 Hz
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 15
Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set
prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to
initiate the setting change). In production systems these bits should be configured with the desired values
prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock.
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