CS2200-OT Datasheet, PDF (7/23 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T_A = -10°C to +70°C (Commercial Grade);
T_A = -40°C to +85°C (Automotive-D Grade); T_A = -40°C to +105°C (Automotive-E Grade); C_L = 15 pF.
Parameters
Symbol
Conditions
Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL
f_XTAL
RefClkDiv[1:0] = 10
8
-
14 MHz
RefClkDiv[1:0] = 01 ¹⁶
-
28 MHz
RefClkDiv[1:0] = 00
32
-
50 MHz
Reference Clock Input Frequency
f_{REF_CLK} RefClkDiv[1:0] = 10
8
-
14 MHz
RefClkDiv[1:0] = 01 16
-
28 MHz
RefClkDiv[1:0] = 00 32
-
56 MHz
Reference Clock Input Duty Cycle
Internal System Clock Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
D_{REF_CLK}
f_{SYS_CLK}
f_{CLK_OUT}
t_OD
t_OR
t_OF
t_JIT
(Note 5)
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note 6)
(Notes 6, 7)
45
-
55
%
8
14 MHz
6
-
75 MHz
45
50
55
%
-
1.7
3.0
ns
-
1.7
3.0
ns
-
70
- ps rms
-
50
- ps rms
Wide Band JItter (100 Hz Corner)
(Notes 6, 8)
-
175
- ps rms
PLL Lock Time - REF_CLK
t_LR
f_{REF_CLK} = 8 to 75 MHz
-
Output Frequency Synthesis Resolution (Note 9)
f_err
0
1
3
ms
-
±0.5 ppm
Notes: 4.
5.
6.
7.
8.
9.
f_{CLK_OUT} is ratio-limited when f_{CLK_IN} is below 72 Hz.
f_{CLK_OUT} = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS842F3
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