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CS2200-OT Datasheet, PDF (18/23 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer | |||
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6.3.3
CS2200-OTP
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven âlowâ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
âPLL Clock Outputâ on page 13
6.3.4
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0]
000
001
010
011
100
101
110
111
Application:
M2 pin function
Disable CLK_OUT pin.
Disable AUX_OUT pin.
Disable CLK_OUT and AUX_OUT.
RModSel[1:0] Modal Parameter Enable.
Reserved.
Reserved.
Reserved.
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
âM2 Mode Pin Functionalityâ on page 15
18
DS842F3
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