CS2200-OT Datasheet, PDF (10/23 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

CS2200-OTP
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
f_L  f_RefClk  f_H where:
f_L
=
f_{CLK_OUT}

3---1--
32
+
15kHz
= 12.288MHz  0.96875 + 15kHz
= 11.919MHz
and
f_H
=
f_{CLK_OUT}

3---2--
32
–
15kHz
= 12.288MHz  1 + 15kHz
= 12.273MHz
CLK__OUT Jitter
180
fCLK__OUT *32/N
160
140
120
100
80
-15 kHz
+15 kHz
60
40
20
-80
-60
-40
-20
0
20
40
60
80
Normalized REF__CLK Frequency (kHz)
Figure 4. REF_CLK Frequency vs. a Fixed CLK_OUT
Referenced Control
Parameter Definition
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 18
5.2.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 5. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
XTI
XTO
40 pF
40 pF
Figure 5. External Component Requirements for Crystal Circuit
5.2.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or terminated through a 47 k resistor to
GND.
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DS842F3