CS42436_06 Datasheet, PDF (61/62 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 6-out TDM CODEC

14.ORDERING INFORMATION
CS42436
Product
Description
Package
CS42436
6-in, 6-out, TDM CODEC
for Surround Sound Apps
52L-MQFP
CDB42438 CS42436 Evaluation Board
-
Pb-Free
YES
-
Grade
Commercial
Automotive
-
Temp Range Container
-10° to +70° C
Rail
Tape & Reel
-40° to +105° C
Rail
Tape & Reel
-
-
Order #
CS42436-CMZ
CS42436-CMZR
CS42436-DMZ
CS42436-DMZR
CDB42438
15.REVISION HISTORY
Revision
A1
A2
PP1
PP2
F1
Changes
Initial Release
Corrected I²C Address in Section 5.7.2 on page 36.
Corrected Chip I.D. in Section 7.2.1 on page 41.
Initial Preliminary Product (PP) Release subject to legal notice below.
Added pin numbers to “Typical Connection Diagram (Software Mode)” on page 11 and “Typical Con-
nection Diagram (Hardware Mode)” on page 12.
Changed ADC Double-Speed Mode parameters. See Note 2 on page 13 and Note 18 on page 21.
Added ADC3 MUX Interchannel Isolation characteristic in “Characteristics and Specifications” beginning on
page 13.
Changed ADC Passband Ripple maximum specifications for SSM, DSM & QSM in section “Characteristics
and Specifications” beginning on page 13.
Changed DAC Frequency Response specifications for SSM, DSM & QSM in “Characteristics and Specifica-
tions” beginning on page 13.
Removed ADC Quad-Speed Mode feature. See Note 19 on page 21.
Added section “De-Emphasis Filter” on page 32.
Corrected section “TDM data is received most significant bit (MSB) first, on the second rising edge of the
SCLK occurring after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is
transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted
on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the
time slot. Valid data lengths are 16, 18, 20, or 24.” on page 33.
Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB to -64 dB) in register “AINX
Volume Control (AINX_VOL[7:0])” on page 48.
Removed the register “Status Control (address 18h)”. See “CLOCK ERROR (CLK ERROR)” on
page 49 and “ADC Overflow (ADCX_OVFL)” on page 49 for the Active Mode setting.
Corrected Figures 21-23.
Added “Ordering Information” on page 61.
Updated temperature and voltage specifications in the “Recommended Operating Conditions” on page 13.
Added test conditions to the Analog Input and Analog Output Characteristics tables.
DS647F1
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