CS42436_06 Datasheet, PDF (33/62 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 6-out TDM CODEC

CS42436
Gain
dB
0dB
-10dB
T1=50 µs
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 13. De-Emphasis Curve
5.4 System Clocking
The CODEC serial audio interface ports operate as a slave andaccept externally generated clocks.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be
an integer multiple of, and synchronous with, the system sample rate, Fs.
5.4.1
Hardware Mode
The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode.
The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 5 for the required frequen-
cy range.
Ratio (xFs)
MFREQ
Description
SSM DSM QSM
0 1.5360 MHz to 12.8000 MHz 256
N/A
N/A
1 2.0480 MHz to 25.6000 MHz 512
256
N/A
Table 5. MCLK Frequency Settings
5.4.2
Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFREQ[2:0])” on page 43.
5.5 CODEC Digital Interface
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with varying
bit depths from 16 to 32 as shown in . Data is clocked out of the ADC on the falling edge of SCLK and
clocked into the DAC on the rising edge.
TDM is the only interface supported in Hardware and Software Mode.
5.5.1
TDM
TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring
after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted early,
but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling
edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot.
Valid data lengths are 16, 18, 20, or 24.
SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample rate, Fs.
DS647F1
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