CS42436_06 Datasheet, PDF (29/62 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 6-out TDM CODEC

5.2.3
CS42436
Hardware Mode
Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup.
Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 for ADC3 set-up options.
Refer to Figure 10 on page 28 for the internal ADC3 analog input topology.
Configuration Setting
ADC_SDOUT
(pin 13)
AIN5_MUX
(pin 1)
47 kΩ Pull-down
X
47 kΩ Pull-up
Low
47 kΩ Pull-up
High
AIN5 Input Selection
Differential Input (pins 50 & 49)
AIN5A Input (pin 50)
AIN5B Input (pin 49)
Table 3. AIN5 Analog Input Selection
Configuration Setting
ADC_SDOUT
(pin 13)
AIN6_MUX
(pin 2)
47 kΩ Pull-down
X
47 kΩ Pull-up
Low
47 kΩ Pull-up
High
AIN6 Input Selection
Differential Input (pins 52 & 51)
AIN5A Input (pin 52)
AIN5B Input (pin 51)
Table 4. AIN6 Analog Input Selection
5.2.4
Software Mode
Single-Ended Mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the
AINx_MUX bits. See register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44 for all bit se-
lections. Refer to Figure 11 on page 31 for the internal ADC3 analog input topology.
5.2.5
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS42436 with the high-pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
5.2.5.1 Hardware Mode
The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode. The high pass
filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.
5.2.5.2 Software Mode
The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3 can
be independently enabled and disabled. The high-pass filters are controlled using the HPF_FREEZE
bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44.
DS647F1
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