CS22250 Datasheet, PDF (6/32 Pages) Cirrus Logic – WIRELESS 10BT CONTROLLER

3.1 Embedded ARM core and System Support Logic
The processing elements of the CS22250 include the ARM7TDMI core and its associated
system control logic. The ARM processor and system controller consist of a memory
management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt
controller, and 2 general purpose timers. The ARM processor and integrated system
support logic provide the necessary execution engine to support a real time multi-tasking
operating system, the network protocol stack, and firmware services.
Memory Management UnitThe ARM instructions and data are fetched from system
memory per “cache-line” (4/8 – Dwords /Programmable) when caching is turned on.
During a cache line fill, critical word data, i.e., the access that caused the miss, is
forwarded to the ARM and also written into the data RAM cache. The non-critical words
in the line fetched following the critical word are then written to the cache on a Dword
basis, as they become available.
Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write
posts use the sequential addressing feature on the memory bus. With dual buffering, an
out-of-sequence write will post to one write buffer while the other buffer is flushed to
memory.
There is one 8Dword read buffer in the MEM block. The buffer is used for both cacheable
and non-cacheable memory space.
Interrupt Controller
The Interrupt Controller provides two interrupt channels to the ARM processor. One
interrupt channel is presented to the ARM on its nFIQ and the other channel is presented
on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both
channels operate in identical but independent fashion. The FIQ channel has a higher
priority on the ARM processor than the IRQ channel.
The Interrupt Controller includes a CONTROL register for each logical interrupt in the
ARM Complex. The CONTROL register serves the following main purposes:
• Provides the mapping between the EXT_INT inputs (physical interrupts) and the
logical interrupt
• Selects the particular type of signaling expected on the EXT_INT inputs: level, edge,
active level high/low, etc.
• Enables or disables a logical interrupt
CS22250 Wireless 10BT Controller
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