CS22250 Datasheet, PDF (18/32 Pages) Cirrus Logic – WIRELESS 10BT CONTROLLER

NOSWAIT
OSRNW
OSCLK
NOSRESET
OSCTLDIR
OSREQ
Input
The wait bus is a single bit bus, which indicates the processing element
addressed on the external control address space is not capable of
completing the transfer on this cycle.
Output
External control bus read/write.
Output
External control bus clock. This clock is half the frequency of the internal
control clock. External processing element clocks the input data to the
OSAD bus on this clock edge.
Output
External control bus reset.
Output
External control bus direction control. The direction bus is a single bit
bus, which indicates the direction of the tri-state drivers on the
address/data bus. A logic ‘0’ on this bus indicates the tri-state drivers are
on source mode on the OS bus and a logic ‘1’ on this bus indicates the
tri-state drivers are on receive mode from the OS bus.
Output
External control bus request. It indicates a transfer has been initiated,
addressed to the external control bus address space. The external
control bus FUB shall de-assert the transfer request on the next OS
cycle, if the OS wait signal is not asserted by the processing element on
the OS bus during the data phase.
OSNINT
This is the interrupt for external bus interface to the ARM core.
Input
External DMA Interface
DMAREQA
DMAREQB
Input
DMA request channel A. When driven HIGH, this signal tells the DMA
controller that an agent on the external control bus is requesting a DMA
access.
Input
DMA request channel B. When driven HIGH, this signal tells the DMA
controller that an agent on the external control bus is requesting a DMA
access.
CS22250 Wireless 10BT Controller
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DS551PP2 Rev. 3.0