CS22250 Datasheet, PDF (27/32 Pages) Cirrus Logic – WIRELESS 10BT CONTROLLER

Table 6. DC Characteristics
Symbol Parameter
Condition
V_IL
Voltage Input Low
V_IH
Voltage Input High
V_OL
Voltage Output Low
I_OL = 800 µA
V_OH
Voltage Output High
I_OH = 800 µA
I_IL
Input Leakage Current
V_IN = V_SS or V_DD
I_OZ
3-State Output Leakage Current V_OH = V_SS or V_DD
I_DD
Dynamic Supply Current
V_DD = 3.3V
I_EE
Note 1
V_DD = 1.8V
Min
-0.50
0.7 * V_DD
V_SS - 0.1
-10
-10
Typ.
22
123
Max Units
0.3 * V_DD V
V_DD + 0.3 V
V_SS + 0.1 V
V
10
µA
10
µA
mA
5.1 AC Characteristics and Timing
Table 7. System Memory Interface Timings
Parameter
t_dSMD
t_dSMA
t_dSMDQM
t_dSMNCS
t_dSMNWE
t_dSMCKE
t_dSMNCAS
t_dSMNRAS
T_perSMCLK
T_suSMD
T_hSMD
Parameter Description
SMCLK to SMD[31:0] output delay
SMCLK to SMA[11:0] output delay
SMCLK to SMDQM[3:0] output delay
SMCLK to SMNCS[1:0] output delay
SMCLK to SMNWE output delay
SMCLK to SMCKE output delay
SMCLK to SMNCAS output delay
SMCLK to SMNRAS output delay
SMCLK period
SMD[31:0] setup to SMCLK
SMD[31:0] hold from SMCLK
Min
Max Units
7
ns
4.7
ns
5.1
ns
4.1
ns
4.5
ns
4.3
ns
4.0
ns
5.0
ns
72
103
ns
1.0
ns
2.4
ns
Notes:
1.
2.
Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf
on SMCLK, SMNCS, and SMCKE.
An attempt has been made to balance the setup time needed by the SDRAM and the setup needed
by CS22210 to read data. If there is a problem meeting setup on the SDRAM, there is a
programmable delay line on SMCLK which can help meet the setup time. Care must be taken,
however, not to violate the setup on the return read data. The delay can be increased by a multiple
of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay.
CS22250 Wireless 10BT Controller
27 of 32
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DS551PP2 Rev. 3.0