CS42516_05 Datasheet, PDF (54/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
SW_CTRL1 SW_CTRL0
0
0
0
1
1
0
1
1
UNLOCK
X
X
0
1
0
1
Description
Manual setting, MCLK sourced from PLL.
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.Auto switch, MCLK
sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
Table 12. Master Clock Source Select
6.7.5 FORCE PLL LOCK (FRC_PLL_LK)
Default = 0
Function:
This bit is used to enable the PLL to lock to the S/PDIF input stream or the SAI_LRCK with the ab-
sence of a clock signal on OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will
be disabled and the SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h)
(Read Only) register contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the
DE-EMPH[1:0] bits to properly apply de-emphasis filtering.
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only)
7
6
5
4
3
2
1
0
RATIO7(2¹) RATIO6(2⁰) RATIO5(2^-1) RATIO4(2^-2) RATIO3(2^-3) RATIO2(2^-4) RATIO1(2^-5) RATIO0(2^-6)
6.8.1 OMCK/PLL_CLK RATIO (RATIOX)
Default = xxxxxxxx
Function:
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
6.9 RVCR Status (address 08h) (Read Only)
7
6
5
4
3
2
1
0
Digital Silence AES Format2 AES Format1 AES Format0 Active_CLK RVCR_CLK2 RVCR_CLK1 RVCR_CLK0
6.9.1 DIGITAL SILENCE DETECTION (DIGITAL SILENCE)
Default = x
0 - Digital Silence not detected
1 - Digital Silence detected
Function:
The CS42516 will auto-detect a digital silence condition when 1548 consecutive zeros have been de-
tected.
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DS583F1