CS42516_05 Datasheet, PDF (13/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to
5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 17)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc
-
Fall Time SCL and SDA
t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
(Note 18)
t_ack
-
Max
100
-
-
-
-
-
-
-
-
1
300
-
(Note 19)
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes:
17. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
--------1---5----------
256 × Fs
for Single-Speed Mode,
--------1---5----------
128 × Fs
for Double-Speed Mode,
-------1---5--------
64 × Fs
for Quad-Speed Mode
RST
t _irs
Stop
Start
SDA
t _buf
t _hdst
t _high
Repeated
Sta rt _{t rd}
t _hdst
Stop
t _fd
t _fc
t _susp
SCL
t
low
t
hdd
t _sud t _ack
t _sust
t _rc
Figure 3. Control Port Timing - I²C Format
DS583F1
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